Introduction

In a previous chapter, I've introduced my current source design that I intend to use to drive the X and Y select lines in my core memory. At that time I led you down the gauntlet of how I arrived at the load-switch design for the inhibit drivers. Now, building on those foundations, let's look at the X/Y line drivers!

Refresher

I've introduced you to the actual topology used to drive the X/Y lines in a previous chapter. There, I had this diagram:

However, if you consider just one line (and it's column and row-drivers), you see a simple H-bridge. And a couple of diodes. In fact, if I design the drivers the same was as DEC did, I would end up with a diode in series with every drive transistor, and the single-load schematic would become something like this:

A simple H-bridge, driving the load through a current source. I also established before that my best guess for a load model is a resistor, though of course I can be wrong about that. At any rate, I'm going to use that for now. The positive thing about that is it's value is something I can easily measure with a DVM.

The matrix configuration puts an limitation on us: in the complete circuit each power BJT needs to be driven by it's own drive circuit. Normally, it would be possible (in this simple setup for instance) to tie TL and BR together. Or if not completely together, at least share some parts of the drive logic. That's not going to work for the matrix setup, so I'm not going to prioritize circuit ideas that afford that. Even if they make sense in an H-bridge, it's useless for our use-case.

One final distinction we have to cognizant about: our source is not producing a voltage, but a current. Of course, it is not an ideal one, it's limited to about 20V output voltage, after which the current drops (that's the reason we can turn it off to begin with). Still, that means that the top-side of our H-bridge is not at a constant potential. It's roughly at 20V when the switch is off, but would drop to a lower value when current is driven through the load.

Previously...

In the last chapter, I described my troubles getting a simple load switch working with a current source. I'm not going to repeat all I wrote there, just the conclusion: we want to use BJTs as switches and we want to avoid driving them into saturation. That's the key to have good control over the load current and fast response times. Taking that idea and even the circuit from there, we would end up with the following high-side drive:

A bit of an eye-chart, but really there's not much new there. It's a copy of the final load-switch design for the inhibit drivers, only replicated twice and stuck on the top-side of the bridge. Fine. But what to do about the bottom side?

Bottom-side drive, first attempt

If you looked at the previous picture in detail, you will see something strange: it's using PNP transistors on the bottom as well as on the top. This is highly unusual. The normal thing would be to use NPN types on the bottom. Those can be easily turned on by driving their base to voltage higher then the threshold voltage. Let's take a look at the following diagram to get a hold of the problem:

When we want to turn the transistor on, we drive current into it's base, by opening the base-emitter diode. That's why we need to elevate the base potential to about 0.6V. However, once the transistor starts to conduct, it's collector-emitter voltage drops to a relatively low value. That in turn means that the collector-emitter diode is forward biased, and if the base voltage is even just a bit higher than it should be, it opens up the base-collector diode as well and we land in saturation.

The drive circuit needs to prevent that. One could simply take the PNP drive circuit I already have and create a complementer design for it. In fact, by knowing that the emitter is grounded, the design can even be simplified. It would look something like this:

The trouble is that this circuit can't really drive the output all the way to 0V. This can be verified by looking at its DC transfer function:

This is a problem: the drive circuit can't turn the low-side off. To make it work, I would need a negative power supply, which I really don't like.

Bottom-side drive, second attempt

So that doesn't work (well), but what how does using a PNP device help? Let's take a closer look of the environment of the bottom-side transistor:

Q23 has its collector grounded and its emitter connected to the middle of the bridge. To turn the transistor off, I need to drive its base to a higher (or at least not more than about 0.6V lower) voltage than its emitter. The bridge center will never be higher than 20V, in fact will never be higher than about 19V due to the series diodes (D7 and D8). So, if I can drive the base all the way up to 20V (or so), Q23 is guaranteed to be off.

To turn it on, I just need to drive the base to a low voltage. In order to drive it into saturation however, I would need to lower the base below ground, something that I can't do without a negative supply. So, almost by definition, this configuration cannot be driven into saturation. Great! I can simply drive the base with a 20V amplitude logic signal and be done with it. So let's talk about that a little!

Level shifters

This is a topic I neglected to cover in the previous chapter about inhibit drivers. That write-up got long enough so I didn't want to go into the details right away. Still, we have the problem that the digital logic in the computer is operating from 3.3V and the bridge (or inhibit) driver circuit needs 20V amplitude control. We need level shifters.

Here is the basic design I came up with:

The first two transistors (Q97 and Q96) are just a regular inverter and technically aren't even part of the level shifter. I included them to make the input waveform realistic, instead of just an idealized voltage source. Q98 and Q99 form another inverter-ish circuit, but it's of a complementer design. The resistor divider (R122/R123) on the input is stiffened (so I'll have to check for high currents there) relative to the normal 3.3V brethren and the output driver (Q99) is connected to the 20V power supply through it's pull-up resistor. This pull-up is increased to 1k instead of the 100 ohms of the 3.3V variant. This is needed to keep the collector current of Q99 within limits.

Which brings up an immediate problem: yes, this is a level shifter, but its a poor one. It can't drive any significant current on its output. This would result in very slow response times in most circumstances. To get around that problem, a second driver stage is needed. I concocted the following design:

The first half of the design is the same as above. The second half is a complementer push-pull driver (Q46, Q48), each made saturation-free by their associated schottky diodes. The first two transistors comprise an appropriate emitter-coupled drive-stage for each of the output transistors. Their output resistor-divider has a capacitive bypass to improve rise and fall times. The input being emitter coupled means that very little current is needed, so the junky level shifter is capable of driving it. The push-pull output means it can drive significant currents to its load in both high and low voltage levels. R45 and R46 provide some emitter degeneration, but more importantly they reduce the shoot-through current on the drive-stage during transitions. Here is the step-response of the circuit:

The green is the input signal, red is the output. Blue shows the output of Q55, the first level-shifted node. You can see ~35ns rise and fall-times with another 20ns or so delay on the rising edge. The delay on the falling edge is only about 10ns. You can also see that the whole circuit (all 8 transistors) exhibit inverting behavior. As I have said, the first two transistors form an inverter and are only there to make the input signal less ideal, so if we ignore that, the level shifter itself is not inverting.

In terms of complexity (again, ignoring the input inverter), this design needs 6 transistors, 3 diodes and 11 passive components. Not cheap, but the best I could come up with.

The last important point is this: since the output stage BJTs never go into saturation, the output signal is not clean: it neither reach the 20V power rail nor ground. There's about 800mV delta. This is another important reason for not using NPN switches in the bridge: the elevated output voltage is enough to turn on an NPN transistor even when the output signal is logic low. The ~~19.2V high output however is good enough to not to turn on a PNP drive, mostly because of the 1V drop on the diodes.

Putting things together

With having both a low- and high-side drive, we can assemble the whole bridge. I set up the control signals such that they drive a 200ns read pulse followed by a 200ns write pulse. There is 300ns delay between these pulses. This waveform is pretty close to what would happen in real life as well. Though I don't know how wide the read and write pulses are going to be, the cycle time is 500ns and reads and writes are always paired up in a ferrite core memory.

The expectation is that during the read, current should flow through the load in one direction, for writes it should flow in the other direction.

I sweep the temperature during the simulation in three steps: 0C, 25C and 50C. For each temperature the current source sets a different target current. What is interesting to see is how fast the current rises and falls on the load, are there any over- or undershoots, oscillations or other irregularities. What is the delay of the whole circuit during both turn-on and -off? So, to start off, let's run a simulation and plot the load current:

Here you can see the (3.3V) control signals for read and write respectively as well.

The results are awesome! There is about 50ns turn-on and 30ns turn-off delay, but these are more or less compensated by the different rise- and fall-times. So, overall, the current reaches it's target value (the half current or zero) in about 70ns from command.

There is a bit of an overshoot during turn-off, but that's not a big deal and the ring-off is quick. The delays are not sensitive to temperature all that much, so sense timing during reads should be relatively easy to accomplish.

Shoot-through

Now let's put the source current on the same graph!

That's weird! It should (apart from polarity) be the same. Yet, the rising edge is earlier and shows ringing in one of the cases. What gives? That current exits the source, but doesn't reach the load. Where can it go? Some investigation reveals it to be shoot-through current in the bridge. In the next diagram, I'll put on the high-side diode currents as well:

So, the top-side of the bridge is conducting on the same half as the bottom-side does during the turn-on. Current flows through (depending on the cycle) the left- or the right-half of the bridge, bypassing the load. The transient lasts about 50ns, but it's relatively significant, about half of the peak current.

This is not nice, but is this a problem? Technically, it shouldn't matter: the shoot-through current is limited to whatever the current source can supply, and that current is the operating current for every power component in the bridge. They should be able to survive it. Same goes to the current source: it should be capable of handling this current. So really the only problem is increased power consumption, but the impact is pretty low due to the short duration of the pulse.

What causes this shoot-through? Let's plot the base-emitter voltage on one the high-side BJTs (Q20) and zoom-in on the shoot-through:

This is the problem: the high-side BJT indeed opens up during the transition. In fact, and this could be even more problematic: it is somewhat opened during the off period too (look at the left-side of the plot). The top BJTs are gently pulling the load to high on both sides during the off-period, then fight the low-sides for a short bit even harder during the transition. Eventually, as the emitter voltage (due to the current source going into regulation) drops, the base-emitter voltage drops sufficiently low to cut off the high-side current, ending the shoot-through condition.

Again, not nice. But is this a problem? In an H-bridge, not necessarily, but remember: we're not in an H-bridge. We are in a driver matrix. Looking back at the matrix setup:

We see that we really are dealing with half-bridges. Since the shoot-through is happening within a single half-bridge (the low-side BJT turning on and the high-side of the same half momentarily conducts), I don't think the matrix setup matters. We see the shoot-through, it increases power consumption (and heating) slightly, but no other feathers would be ruffled. Not certain the extra current is to the point where it matters.

Are we done?

I think so, but there was a time in my life when I really wanted to get rid of this shoot-through. The technique I came up with was to build the high-side out of the complementer circuit: NPN power stage and the associated changes in the driver:

The idea here is that the power stage gets shut off whenever the base drive is lower than the emitter (the load) can ever get. That is easier to achieve because of the series diodes (D34 and D35 on the left half of the bridge for instance). These are silicon diodes, guaranteeing more than a volt of drop. These are necessary for the matrix setup to work and are provided on the same board as my core mat is mounted on, so it's inherently part of my circuit and I can't change it. Let's look at the interesting currents in this circuit!

Here the blue curve is what the load sees and the green one is what the current source supplies. The shoot-through is indeed completely gone, but is replaced by some unaccounted for load current after turn-off. Not a big deal, the amplitude is small enough to be harmless. This current is going through the base of the high-side BJTs and is needed to charge up the parasitic base-emitter capacitor inside the transistor. This becomes obvious if we plot the base-emitter voltage and the emitter-current on the high-side BJT:

The potentially bigger problem is that the top of the pulse is not flat: it keeps rising even after the full 200ns has passed; in fact only reaching about 95% of the nominal value by that point.

I can't really explain this phenomena at this point. I think the shoot-through actually helped kick the current regulator out of its slumber a few tens of nanoseconds earlier and that's what's responsible for the nice, flat tops in the previous circuit.

Summary

Let's call it a day here and take stock of what we've got! I presented two functional H-bridge solutions. One suffers from shoot-through, the other from slow settling of the target current.

Complexity wise the are both identical. To drive a single power BJT, we need 6 other transistors along with a bunch of other circuit elements. That's a lot. The X (or Y) matrix in my memory is 16x8, meaning I have (16+8)*2=48 power BJTs. That's 366 transistors for the X matrix; 672 total for the core memory. Pretty large. On top of this, we have 32 inhibit current switches (also 6 transistors per power BJT), so the total is around 900 transistors.

I will try to figure out how to make the non-overshoot variant work better for flatness. If I succeed, I think I will prefer that configuration. If I can't, I think I will just live with the shoot-through and vote for the first design.

Lastly, I just want to note how crazy this journey was, including its end-point. I spent weeks and weeks and weeks banging my head against this problem. I detailed many of the false-starts in my write-up about the inhibit switches, here I spared you from that. But believe me! This wasn't a straight shot to success.

And about the end-point? Look at the latest design I presented: the high-side ended up using NPN transistors while the low-side turned into PNP ones. The exact opposite of what an H-bridge should look like! This certainly is the craziest bridge I have design, or indeed have seen in my life.

So. Where to go from there? There are two more thing I need to cover before I can tie a bow on the core memory subsystem: I need to design the address decoding logic and figure out the timing sequencer. These I will cover in the next few chapters. But for now, I'll need a drink.