Introduction

I've said I'm not interested in designing my own power supplies. Well, now that I spent several days doing just that, I think I have to explain myself.

There are many, many, many tutorials online on switching power supplies, both theory and application, I'm not going to write yet another one here. Instead, I'll describe what I have found while exploring the cul-de-sacs and dead-ends of this wretched corner of electronic engineering.

So, buckle in, let's start!

What do I need?

This is actually a good starting point. Why am I doing this? Now, that the design of most of the sub-circuits start to take shape, I can fairly confidently tally the power rails and their basic properties in the disintegrated machine. I need +/-15V for the sense amplifiers, 3.3V for the digital logic and 20V for the core current sources. The highest of these is 20V, so it makes sense to base the rest on this supply. It also happens to be a voltage level that many laptops use. (More or less, Sony uses 19.4V for instance. Still, close enough.) That means that high-current, cheap power bricks are abound.

I expect my machine to take about 150W in digital logic and another 50-100W for the rest. The problematic one of these is the 150W on the 3.3V rail: that is on the order of 50A of current. Ouch! That's something you can spot-weld with. A 50A step-down converter is not easy to get (this is multi-phase, synchronous converter territory), but I'm also not looking forward to distribute 50A of current in the PCB. So, what's the alternative? Well, I can distribute 20V instead. The corresponding current is only 7.5A at that voltage, make it 10A for losses, which is manageable. The problem of course is that my logic doesn't run at 20V, it runs at 3.3. So, getting 20V close-by doesn't get me anywhere, I still need to down-regulate to 3.3V, only now in a distributed manner. This technique is called point-of-load regulation and is quite common. This way, I need lower current regulators (I'm thinking 5A or so) and have many copies of it, all over the design.

Now, here's the rub: if I want to embed a dozen or so 3.3V regulators in my otherwise transistorized design, it starts looking rather ugly to use something modern for this purpose. Thus the quest: let's design a 5A, 3.3V buck converter using discrete transistors. It should have relatively high efficiency, it should be capable of running off of 20V. It should work across temperature (of course), and have good load regulation. This later one is important: the power consumption of the load is very time-dependent, there are switching currents as well as static currents that depend on the logic levels, so as the circuit operates, the current demand will change radically. If I don't regulate the load well enough, there will be cross-talk between the logic components through the power rail, which can (and with my luck will) result in very difficult to track down heisenbugs. Supply regulation is less interesting as I expect the upstream 20V to be regulated, but transients will appear on that supply for sure as well, so I can't completely ignore that aspect either.

The final thought is this: once I have a 3.3V buck regulator design, it should be fairly simple to modify it to make a +/-15V inverter out of it, especially if I keep that application in mind.

What did others do?

This is a good place to start: can I just rip off an existing design? There are a few switching power supply projects out there in the wild, that use discrete transistors. There's Roman Blacks two-transistor design. There's SAGI universes buck converter. I'm sure there are others too.

I've modeled both of them in LTSpice to play around with them, but I had trouble (lots of trouble in fact) to get them going. Roamns design doesn't really scale to large loads, or to be precise, it doesn't work with both light and heavy loads. The SAGI design uses an astabil multivibrator as its local oscillator, which suffers from startup difficulties.

Both designs use proportional feedback, which is to say that the output voltage adjustment is a bit difficult. This is the least of my problems though.

I had a hard time keeping either design even oscillating, let alone regulating over the full -25...125 temperature range. Granted, I don't need that, but I do need a robust power supply and this points to infirmities that bound to rear their ugly heads at some point during the project.

Worse, the output voltage is rather temperature dependent even though they both use zener diodes as references. The problem is that the zener isn't directly compared to the output voltage, there's at least one Vbe drop involved, which itself is rather temperature sensitive.

Neither design has short-circuit or over-current protection and at least one of them suffer from output voltage overshoot during start-up (I don't remember which one).

Neither design has a fixed switching frequency, which makes component selection and output ripple control difficult.

Being such simple designs, one can't really fault them for these problems, it's just that they need a lot of work to make them meet my requirements.

And if I were to put a lot of work into it, I might as well start from my own ideas.

The basic idea: Hysteretic regulator

This is one of the simplest designs possible. The linked TI document gives a good overview. I started with a simple Schmitt trigger circuit:

This is an idea ripped from the internet, not my original. In this particular variant, I'm using D11 and D8 to speed up the common-collector stages. The magic is in R27, which, when Q12 conducts increases the threshold voltage of Q11, thus creating the output-dependent threshold voltage that's the key feature of any Schmitt trigger design.

The input to this circuit would be the error signal. The output would control the switching element. Since the threshold voltage depends on the voltage supply, I would not want to operate this from the input 20V logic, so a simple linear regulator would be needed to create a stable VCC supply voltage. This means that I'll need to level-shift the output before I can drive the switch. Talking about a switch, the easiest thing to do is to use a PNP transistor for switching purposes as that's easier to turn on. The problem there is that the PNP switch needs the same polarity signal as the output of the Schmidt trigger and level-shifters normally invert. This means another inverter stage to get things into the right polarity.

The last thing to think through is this: the output of this logic is very sensitive to output current. When Q12 conducts, the output voltage is roughly the same as the threshold voltage, which is determined by the current through R27. This current is the sum of whatever is flowing through R24 and the output. To make this thing work well, it needs a load isolation stage: an emitter-follower.

Putting this all together results in this circuit:

Already at six transistors and we haven't even gotten started. This controller still has so many weaknesses, it's not even funny:

The threshold voltage depends on the Vbe drop of Q1, so it's highly temperature dependent.

Being a hysteretic design, it operates at a fixed output voltage ripple, something on the order of 200mV. Also, as the nature of the any hysteretic design, the operating frequency is not stable and depends - most importantly - the load capacitance. This cannot be easily controlled, and depends on whatever I connect to this thing. Both of these problems can be mitigated by an output LC filter design, but that adds even more, large components to the circuit.

Without careful component selection, L1 can easily go into discontinuous current mode, which means really high peak currents. This can drive the core into saturation, generate heat and, if sized properly for the peak current, leads to unnecessarily large physical size.

This circuit has no over-current or short-circuit protection. In its current configuration, it has relatively low operating frequency too, making further filtering even more challenging.

On the plus side, it can act rather quickly to load changes (which of course will not be the case due to the heavy post-filtering requirements), it is inherently stable and suffers no startup difficulties.

I've tried all four possible switching elements in this design. Here are the results:

• PNP transistors: slow due to saturation, about 3us minimum turn-on time
• NPN transistors: quick, but high power consumption due to emitter-follower setup, about 5W. If used in boost configuration, would be just as slow as PNP.
• PMOS FET: slow due to high gate-charge, about 8us minimum turn-on time
• NMOS FET: fast, but needs boost circuit and not all that power efficient either due to switching losses: about 3W

There is a good reason to chase speed: if I can't increase the switching frequency to about 100kHz minimum the inductor size becomes prohibitive. To reach 100kHz, I need something that can be turned on- and off within 1.5us, ideally in less then 1us to keep minimum duty-cycle under control. (To get from 20V to 3.3V, we need a duty cycle of about 15%.) For BJTs the slow-ness comes from the fact that they operate in saturation mode, and once they enter saturation, it takes a while to turn them off. For MOSFETs the slowness comes from the input capacitance that needs to be charged and discharged during on/off transients. This later one can be remedied externally, if high-enough gate-drive currents can be provided. So let's try to make some MOSFET-based design working!

Switch driver

To make further progress, I think I'll have to start working on a high-voltage, push-pull driver. This should enable the use of either a boost circuit, or, if nothing else, higher-current base/gate drive. After some tinkering, I came up with the following contraption:

For now, let's ignore V4 there and concentrate on the rest of the logic. The first transistor in the chain, Q2 is just an emitter follower in my roll-of-the-mill logic gate configuration. It's there as a placeholder to provide reasonable drive waveforms, not just the ideal voltage source that LTSpice has. The next two transistors, Q1 and Q5 are in the common-emitter configuration (with the schottky speed-up trick) that finish the pre-drive inverter and provide level-shifting at the same time. Their load-resistor (on the collector) is broken up into a voltage divider to provide the appropriate voltage levels for the complementer pair of the push-pull drive stage (Q4 and Q3). These too are prevented from saturation using the same schottky diode trick. Finally, the output of this stage is simply driving the switch element, in this case a PFET.

By providing a low-impedance path for both charging and discharging the gate capacitance of the FET, quick switching and short propagation delay (about 75ns for rise, about 100ns for fall) can be achieved. The bottom resistor on the push-pull drive (R7) is there to strike a compromise between switch time and shoot-through current of the push-pull stage.

Back to V4, for a second: since the switching element, the PFET will turn on for anything a few volts below it's source potential (20V in this case), we don't need the gate driver to travel all the way down to 0V. 15V is sufficient, and, by decreasing the amplitude, we can make the drive go a bit quicker. At least that's the theory.

Almost all components of this needs (and will be) fine-tuned when integrated into the regulator, but to prove it's chops, let's look at a waveform:

Here the input signal (the red one) is 1MHz in frequency. You can see how the switching signal (this is the output of the FET) is lagging a little, but still follows very closely the input.

I think this should work.

Integration

Now, let's rip out the old driver from the hysteretic controller and add this new design:

You see the circuit from the previous section copy-pasted here, with the component values adjusted. The V4 supply is gone, the gate driver goes from GND to the full supply current. I've also changed several other component values, mostly in order to reduce power consumption. Now, let's look at performance!

Here you see the load varying from 50 Ohms (66mA) all the way to 0.5 Ohms (6.6A). The output voltage (after the initial overshoot) settles at 3.3V, which is what I need. More importantly, the final output voltage is independent of load current, which is to say, the regulator regulates. The switching frequency is around 330kHz; high enough to be able to to lower the inductor in the secondary filter (L3) to 33uH and still get only a few mV of output ripple.

One thing that's still a thorn in my side is the artificial load, R5. This dissipates (and wastes) 2W of power. Without it however, the switching frequency increases to more than 2MHz and the regulation becomes very poor (the delay in turning the switch on and off becomes too great to ignore). I'll have to see if there's something I can do about it.

Before we go there, let's look at a few other things!

Temperature dependency

Well, this is not nice. It's almost entirely due to the Vbe change of Q1, which is our comparator. This, I would like to improve, though to be honest the range as-is is acceptable: about 10%.

Load regulation and output impedance

Changing load from 1A to 5A, a 4A step:

The transient lasts about 500us, which would indicate a loop bandwidth of a few kHz. That's bad, and would indicate that a lot of large bypass caps are needed on the output to control the impedance of the power distribution network (PDN). I'm not sure if I did the output impedance analysis correctly (I stuck a current source on the output), but I got a 3dB point at around 3kHz:

Supply regulation:

A 5V step on input voltage:

This is actually surprisingly good: only a ~70mV change on the output for a 5V change on the input. I don't think this needs improvement.

Improving load regulation

I believe the primary order of business is to improve the loop bandwidth of the circuit. The other parameters are in the acceptable range. Here is the problem though: the loop frequency is not determined by the controller at all. It is a hysteretic machine, it's going through the control loop in every cycle. In other words it has a loop bandwidth of about 300kHz in this case. It's the secondary smoothing filter (L3/C3) that causes the problem, In fact, if you calculate the corner frequency of these two elements alone, it comes back at 2.7kHz. This is catch-22. The corner frequency has to be low to filter out the inherent voltage ripple in hysteretic controller, yet it ruins load regulation in the process.

What to do, what to do? Within this topology, not much can be done other than tweaking the component values. Here's where I've gotten:

Notice, how the artificial load (R5) is now gone and the inductor values as well as some resistors are changed. Importantly, the hysteresis setting resistor (R4) is much reduced, so it reduces the inherent ripple. The load regulation improved by more than order of magnitude:

On the negative side of things, the output ripple is increased to about 100mV under light loads. The reason I'm not all that outraged by that is that more filtering is needed to get the load response under control. That inherently will improve the ripple as well.

Local supply

There is one thing that needs to be taken care of: the hysteretic comparator (Q1, Q2) uses an ideal power supply at this point. That's not reasonable. In theory, one could run this part of the circuit from the 20V supply, but that makes the hysteresis, and through that the operating frequency and output voltage of the circuit dependent on the supply. A better idea is to provide a local, stable power supply based on a zener reference. Here's what the circuit looks like:

Q4 provides temperature compensation for the emitter follower (Q3) that provides the regulated 6.2V supply to the comparator.

Temperature compensation

With all these modifications, the temperature dependency of the circuit got rather bad: about 600mV change over temperature (or about 20% of nominal output). Now, to be fair, my logic circuit is not all that sensitive to supply voltage, this would be just fine. What I'm a bit worried about is this: there will be a dozen or so of these regulators sprinkled around the whole computer to provide the sufficient aggregate current. Each on their own temperature, depending on their load and surroundings. This would mean that in the worst case directly communicating logic gates could be operating from voltage supplies that are 20% off of one another. I could characterize the logic gates for this condition to see if it is a real problem, or I could fix the temperature dependency of the supply.

Let's see if it is easy to do! As I have said, the temperature dependency comes mainly from the change in Vbe of Q1. This is what needs to be compensated. After a lot of tinkering, this is the best I could come up with:

You see an extra emitter follower on the input to compensate for the Vbe drop of Q1. This lowers the threshold voltage to close to 0V, which is not good, so the bottom side of the Schmitt trigger is elevated by a voltage supply in the form of Q7. This supply also has a Vbe dependence, so it itself is compensated by an extra emitter follower: Q9.

All this reduced the temperature dependency to about 60mV. With the current settings, the operating frequency is around 700kHz and a second filter stage reduces the voltage ripple on the load to less than 4mV.

hrough all these changes, the initial overshoot improved significantly as well:

and the load regulation got better too: the settling time is on the order of 20us now. Still not stellar, mind you, but acceptable.

Power consumption and efficiency

The main points of power consumption are the power elements: M3 and D12. At 5A load, M3 dissipates about 1.5W, while D12 is burning away 2W. This, while the delivered power is 16.5W, so the efficiency is just north of 80%. Again, not horrible, but could be better. I have to investigate a synchronous topology (replacing D12 with an NFET), as well as fine-tuning the switching frequency and balance output ripple and efficiency.

I looked into this briefly and I don't have anything simple to report. The synchronous design (if done in a straight-forward way) has horrendous shoot-through, so it's a no-go. I would need to do staggered timing of the high- and low-side, something that I'm not looking forward to. At the very minimum, it would require another two transistors to implement a second push-pull drive and some timing network that would need to be tuned.

The operating frequency is - strangely - controlled by the series resistor on the first filter cap (R9). Lowering the resistance value lowers the switching frequency. The power consumption is not really impacted though: as the dissipation on the FET is decreasing, the power on the diode increases more or less cancelling out the gains. Overall, there's maybe an impact of 500mW, if that.

Bells and whistles: over-current protection

This is relatively simple to implement, but takes three extra transistors:

A series sense-resistor (R26) is used to detect the load current (this needs to be before the feedback point so that the control loop compensates out the drop over the sense resistor). Q8 turns on when the drop over R26 is over Vbe, or about 0.6V. This increases the voltage at the 'ovc' node to that of the output voltage - which for this circuit to work needs to be at least about 0.6V. This event in turn triggers Q13 to close, lowering the base of Q14, turning that on as well. When Q14 is on, the base of Q10, the driver of the power stage pre-driver gets pulled high, which - over the drive-stage inversions ends up turning the power FET off. This condition stays, until the output current (and drop through R26) drops below Vbe, when all these clamp components turn off and normal operation resumes. This in turn implements another control loop which in effect limits the output current to a set value. The current limit is quite a bit temperature dependent, so it's a blunt instrument, but that's OK: it is a safety feature only. With the current component selection, the current limit is around 3.75A and can be set by selecting the appropriate value for R26.

Bells and whistles: soft-start

Since I will have several of these converters in the design, it would be nice to control the turn-on ramp of each of them. Without this, the in-rush current of all the regulators - especially turning on simultaneously - can result in all sorts of problems, including triggering the current limit or short-circuit protection of the upstream converter and/or browning out the main supply.

This is not a unique problem to my design, it's a general problem with power supplies. The solution is called a "soft-start circuit" and almost all modern regulators have support for it. Essentially it slowly ramps the output voltage (or current) of the regulator upon turn-on to give time for all the downstream capacitors to charge up, preventing large current spikes. There are several techniques to achieve this, the two main ones are: (a) ramping the current limit of the regulator gradually from zero, resulting in current-limited operation during startup and (b) ramping the reference voltage from zero, resulting in the regulated output voltage to slowly change during startup.

I'm going to go down the route of mocking with the reference voltage, mainly because I couldn't find a simple way to mess with the threshold level of the over-current protection.

For me, the reference voltage is the threshold voltage of Q1. This - after my temperature compensation efforts - is controlled by Q7, which is in the emitter-follower configuration. Its emitter voltage is what sets the reference voltage. So, what we need to do is to lower this point in the circuit to 0 and allow for it to slowly ramp during startup. Here's the contraption I came up with:

Q15 clamps its output (collector-emitter) during startup and slowly turns off as C4 (through R30) charges up. With the currently selected components, the turn-on transient looks like this:

The spikes there are due to the load-steps I'm introducing (3A to 1A and back). I kept it in the simulation to make sure that no ill-effects on load regulation are present.

You can see that there is a turn-on delay of about 4ms and the ramp lasts on the order of 1.5ms. Of course the component values can be tuned to make this time shorter or longer.

Incidentally, the base of Q14 can also be used as a crude regulator on-off control input. If it is lifted above about 0.6V (let's say 1V to be safe), the regulator will be off (or off-ish, depending on component matching).

The circuit works well all the way up to 100C temperature (with the turn-on ramp slowing quite a bit with temperature):

At 125C the regulator eventually shuts down. This has nothing to do with the soft-start though, there are other things that go funky at such high temperatures (the Schmitt trigger barely works for instance). This is not all that worrisome. If I can only work up to 100C temperatures, that's fine by me. In fact, as I mentioned in other places, the core memory is only specified to operate up to 50C, so this gives me quite a bit of margin.

PDN

Let's think a little more about what is down-stream from this regulator. There will be power traces going to the individual modules; Then, on the modules themselves, there's going to be some de-coupling capacitors to deal with high-speed load-changes. I expect the power traces to be at least 1mm thick. I'm not sure if I will have a solid ground on the back-side of the base board holding the modules, but I will do my best to get there.

The trace inductance for 1mm wide traces on a 1.6mm PCB with a ground plane is 2nH/mm. Twice the thickness, half the inductance. Twice the length, twice the inductance. Let's do some calculations! The switcher is going to be - say - 10-20cm away from the modules it powers, so the impedance (provided I can have a nice ground return, which, as I have said, I might not) is about 200-400nH. With imperfect ground return, this could be much higher, so let's say around 1uH. If you look at the later schematics, that's the inductance I have modeled there.

I certainly can afford at least 10uF of bulk capacitance on each module. Right now I'm planning on a pair of 47uF capacitor on the regulator itself. Again, you see these values reflected in the schematics.

Real capacitors are not the perfect ones that LTSpice simulates though. The two major parasitics to think about are the series resistance (ESR) and series inductance (ESL). These depend on construction, but most importantly package size. So let's look at some typical values:

• Electrolytic cap for 100uF/6.3V has an ESR of ~30mOhm.
• 0603 ceramic cap would have an ESL of 200pH and an ESR of 3mOhm
• 0805 ceramic cap would have an ESL of 300pH and an ESR of 4mOhm
• 1206 ceramic cap would have an ESL of 400pH and an ESR of 1mOhm

I've put these values in the simulation, but without increased resistance, the PDN is very resonant and oscillates like crazy. This is not unheard of, but rarely an issue. I'm not sure why it shows up so prominently in my sims, probably because reality is still not as pristine as my models.

At any rate, increasing ESR is easy: just put a resistor in series with the de-coupling caps. It however is another tuning exercise to get the values right; I have made a guess in the schematics I'm showing here.

When it comes to PCB design, I think I will add pads for a series resistor just to be on the safe side, but default to copper bridges across them: I really don't want to populate so many 0-ohm resistors.

Taking stock

I'm not done with regulators, but let me stop here. I think I have a feature-rich and robust buck regulator design in my hand. It satisfies my requirements in terms of stability, operating frequency and current delivery. It has all the bells and whistles I could think of so I will be confident (after testing in real life of course) to trust my logic circuits on it. I also believe it will be hard to destruct this power supply with f-ing up it's load, such as having a short to ground on the output.

What I'm not all that happy with is the load regulation (i.e. the controller bandwidth), which is the result of the secondary filter (L2 and C2) and is a necessary compromise between voltage ripple and load regulation.

The roughly 80% efficiency is also less then stellar and will require some cooling considerations, especially on the rectifier diode, D12.

Finally, the circuit ended up being rather complex; a far-cry from the simple two- and four-transistor designs I found in the wild. I'm looking at 16 BJT transistors, a power FET, a high-current diode and seven small-signal diodes, not even counting the passive components. Considering I will need a dozen or so of these beasts, these numbers add up quickly. Still, this was the simplest I could come up with and if you hung around with me through this whole journey, you hopefully understand why each and every one of them is necessary.

Next, I will have to discuss the rest of the power supplies, hopefully in a shorter chapter. These include: A fly-back variant of this regulator to generate -20V. Maybe +/-18V. This is needed for the sense amplifiers, although I'm not going to use the outputs directly. Instead I will sub-regulate them down to +/-15 using linear regulators; something that also needs to be designed.

Till that time, happy new year and see you soon!