Introduction

In this article I will describe sense amplifiers for ferrite core memories. This is the second installment of my design for the memory subsystem.

Let's review the main components of a core memory:

We see a set of X and Y drivers. During a read operation these deliver half-currents to one row and one column of the core matrix. These currents are insufficient alone to flip the permanent magnetization of the core rings from '1' to '0', but combined, they are (thus the name "half-current"). There's only one core, at the intersection of the driven X and Y lines where this happens. This core ring, if it was set to '1', will turn to a '0', releasing it's stored magnetic energy. This energy will get coupled into to the sense/inhibit wire, which goes through all cores in the matrix, generating a small voltage spike:

As you can see, the bump is expected to be around 40mV. However, if the core already contains a '0', it still generates some response to the current ramp on the X/Y wire (after all we're looking at a very small transformer here. The size of this response depends on the current ramp rate of the X/Y drivers (dI/dt of the pulse), but if properly handled, should be around 20mV, though I have a hard time believing this number.

The length of the pulse is not well documented and I don't have the memory hooked up at this point to make measurements. My best guess is that it's not shorter than 200ns.

Let's look at the polarity of the pulse next!

You see here that the sense/inhibit wire crosses over at the mid-point. This is done for noise-immunity purposes: half of the cores inducing voltage in one direction, while the other half does it in the other. That's great, but it also means that the interesting pulse (depending on the core selected) can come with either polarity as well. We need a detector that can detect either of these pulses:

Now, we can describe what our sense amplifier needs to do: a bipolar detector with a threshold voltage around 30mV (settable of course), one that's fast enough to detect 200ns long pulses. It needs to present this detection as a logic level signal. It needs to perform well over temperature.

I don't know much about core memories and sense amplifiers. I'm old, but not old enough, I guess. So, I did what any sensible person would do: look up how others did it. Since I have a memory matrix from a PDP-11, the natural place to start was the PDP-11 documentation. I'll link to them at the end of the article, but the important bit here is that, depending on the model, they used either the Motorola MC1540 or the TI SN7520 integrated sense-amplifiers. It should not come as a surprise that neither of these chips are currently available from their respective vendors and their datasheets were scrubbed from their database probably decades ago. Still, the fabulous BitSavers archive has databooks, even an application note from Motorola describing these circuits. Some of the pictures are from these sources.

Out of the two circuits, the Motorola design has more detailed documentation, down to an actual schematic with resistor values marked. So, I decided to start off from that design:

Especially after reading their appnote, the front-end differential amplifier is easy to understand. That is anything leading to pin (14)/1. The rest is a mystery to me, but that's not a problem as long as it works. So, I built it up in LTSpice (yes, I'm back to that, because, again, I'm interested in parameter sweeps, especially of temperature). I've tried it and ... it didn't work. Not completely broken, mind you, the front-end worked beautifully. The part after the aforementioned point didn't. Still, I figured, it's the diff-amp portion that must be the hard part. I can put together a comparator and level-shifter circuit. So, I started fiddling around and came up with the following:

You can see how the first portion is a faithful reproduction of the Motorola design. I've lowered it's gain a little bit, but that's all.

The output Q12 creates the comparator, its emitter set to a reference voltage; Thus it will trigger one Vbe over that reference. To get to said reference, first, a reference current is generated from the current source (Q14/R6) through a current-mirror (Q13/R17). This current is converted to the reference voltage over R19. Finally, the reference voltage is fed through an emitter-follower (Q15), which not only de-couples the load but compensates for the temperature-dependence of Vbe.

The output of the comparator is now a logical signal, but it is all sorts of wrong in terms of voltage levels. The last three transistors are there to step it back to normal logic levels, finally terminating as the output of the emitter of Q10. The diodes strapping some of the transistor collectors and bases create Schottky transistors and improve timing quite a bit.

Performance

First, let's look at the DC transfer function between the differential input voltage and the 'SENSE_OUT' node:

You can see very high gain, and bidirectional behavior: it doesn't matter if the (differential) input is positive or negative, the output goes in the same direction. 0V differential input maps to about 6V output, while the output saturates at around a Vbe lower than the positive supply (12V in this case). This happens for an input voltage of about +/-50mV.

There is some temperature sensitivity to both gain and offset voltages, but the dependency is not horrible.

Now, let's take a look at the input-to-output transfer function:

This is pretty neat: the threshold voltage is set to about 29mV, a realistic value. Zooming in on the transition region, we see this:

About 1mV of uncertainty in the actual threshold value, based on temperature. That's highly acceptable.

Next, let's look at the dynamic behavior of the circuit! I've placed the following input pattern on the input:

This is an ever-increasing train of input pulses. Each pulse has a 50ns rise and fall-time and a 100ns top. Here's how the output looks like:

I zoomed in a little, to make it a bit easier to see. You see marginal response for the 30mV signal (which is where you'd expect marginal behavior), very clean detection of anything taller and no detection of anything small then that. Exactly as expected. You see almost not temperature-dependency either, though, I admit, it's hard to actually see it on these screen-shots.

The propagation delay through the circuit is about 85ns with rise-times around 17ns and fall-times in the range of 25ns. These values are somewhat worse than the original Motorola design, which claims a propagation delay of only 30ns and rise- and fall-times of 20ns. Nevertheless, I think this amplifier should work well for my needs.

What's next?

I plan on thinking about the X and Y drivers and their current sources next. I will probably lump in the inhibit drivers as well: those are similar, but somewhat simpler to implement as they don't need to provide bi-directional currents. Till that time, be well!

Sources

The Motorola design is described in their AN-245A application note and in their (rather spartan) datasheet. TI describes their sense-amplifiers in their respective datasheets.

You can find more information on the PDP-11 memory subsystem here: [https://github.com/andrastantos/the\\\_d\\\_machine/tree/main/docs/core\\\_memory](https://github.com/andrastantos/the_d_machine/tree/main/docs/core_memory)

The simulation model is also checked in to the same repository: [https://github.com/andrastantos/the\\\_d\\\_machine/tree/main/circuit\\\_sims/sense\\\_amp](https://github.com/andrastantos/the_d_machine/tree/main/circuit_sims/sense_amp).